A local MCP server that provides read-only, compiler-backed semantic analysis for Verilog and SystemVerilog projects using pyslang. It can parse filelists or explicit files, report diagnostics, list design units, inspect hierarchy, and find symbol declarations/references within a project root.
From the registry: Compiler-backed read-only Verilog and SystemVerilog project analysis.
$ pip install --pre pyslang-mcphttps://pypi.org/project/pyslang-mcp/Please install the `pyslang-mcp` MCP server into my current AI client (that's you).
Required prerequisites (do these first if not already done):
- **Install Python 3.11 or 3.12** — Python 3.11 or 3.12 is required to run the server.
- **Install the pyslang-mcp package from PyPI** — Install the published alpha package from PyPI using pip with --pre. Run: `pip install --pre pyslang-mcp` (https://pypi.org/project/pyslang-mcp/)
Canonical MCP server config (stdio transport):
- command: `pyslang-mcp`
- args: []
Note: Use the PyPI-installed console script as the preferred portable setup. The README also documents an editable checkout path, but the simplest install is `pip install --pre pyslang-mcp`. No environment variables are documented for server startup. Tool calls must provide a `project_root`, and all referenced paths must stay under that root. Although the README mentions an experimental local streamable-http transport, it does not provide canonical installation/configuration details for it, so stdio is the usable documented transport.
Add this MCP server to my current client's config in the correct format for you. If you need secrets or credentials I haven't provided, ASK me — do not invent values or leave raw placeholders. After adding it, tell me how to verify the server is connected.Web scraping with stealth HTTP, real browsers, and Cloudflare bypass. CSS selectors supported.