Head of Device Engineering (Hardware + Embedded)
Explicitly mentions vibe coding and institutionalizing AI-assisted PCB design to boost productivity with verification gates.
About the Role
Lead device engineering for a family of connected consumer devices, owning hardware and embedded end-to-end—from schematics and PCB layout to firmware, low-power optimization, OTA safety, and production readiness. Build and mentor a lean multi-silicon team to deliver 15 SKUs while institutionalizing AI-assisted PCB design and maintainable firmware platforms.
Job Description
Role
Head of Device Engineering (Hardware + Embedded) responsible for end-to-end device delivery for a family of connected consumer products. The role combines hands-on schematic/PCB design, firmware development, lab debugging, production readiness (EVT→DVT→PVT), and people leadership to deliver multiple SKUs across changing silicon choices.
Key Responsibilities
- Own device engineering across schematics, PCB layout, bring-up, firmware platform, low-power design, OTA/DFU, and production readiness.
- Build a multi-silicon firmware platform with portable modules, SoC adapters, and config-as-code (use Zephyr where appropriate; other SDKs as needed).
- Personally drive resolution of hard technical problems such as power drains, BLE instability, field-only bugs, OTA failures, and manufacturing fallout.
- Lead EVT→DVT→PVT activities including calibration flows, factory test firmware, fixture/jig requirements, yield and failure analysis.
- Institutionalize AI-assisted PCB design and “vibe coding” with strict verification gates and measurable productivity improvements.
- Hire and grow a lean device engineering team to meet product and manufacturability targets.
Requirements
- 10–18+ years of experience with multiple shipped embedded products end-to-end across at least two different silicon ecosystems (examples: Nordic, ST, TI, Silabs, Telink-Semi).
- Hands-on schematic and PCB competence using KiCad or Altium; strong layout review instincts (RF, power, DFT/DFM).
- Strong C/C++ and RTOS experience; excellent debugging skills with lab tools.
- Demonstrated low-power design improvements and disciplined regression prevention practices.
- Production OTA/DFU experience and a rollout safety mindset.
Bonus Qualifications
- Experience with LTE/GNSS and MQTT over TLS (relevant to a subset of SKUs).
- Experience with secure boot, signing, provisioning, and secure elements.
Location & Employment Type
- Work location: In person, Mumbai, India. On-site presence required for lab work and EVT/DVT/PVT; specific commute/relocation note for Oshiwara, Mumbai, Maharashtra.
- Job type: Full-time.
Compensation & Benefits
- Pay: ₹1,500,000 - ₹1,800,000 per year (as listed).
- Benefits: Health insurance, leave encashment, paid sick time, paid time off, Provident Fund.