Physical Design Engineer, Forward Deployed Engineering

Role

OpenAI’s Forward Deployed Engineering team is hiring a Senior Physical Design Engineer to act as the team’s SME for semiconductor customer engagements. The role focuses on applying deep backend physical design expertise to shape AI-assisted solutions, advise customers, build lightweight prototypes and benchmarks, and help the team translate high-touch deployments into repeatable production solutions.

Key Responsibilities

• Serve as the physical design SME across semiconductor deployments and advise FDE teams on backend implementation workflows, constraints, and trade-offs.
• Partner with FDEs during customer discovery and scoping to translate ambiguous problems into solution hypotheses, success criteria, and technical plans.
• Support customer-facing technical conversations and engage credibly with technical leaders as a trusted advisor.
• Shape AI-assisted solutions across physical design workflows including floorplanning, place and route, clocking, timing closure, congestion, power, physical verification, and signoff.
• Guide feasibility and integration decisions for design, verification, and physical design across the chip design lifecycle.
• Curate evaluation datasets, golden tasks, rubrics, and acceptance criteria to ensure evaluations reflect real workflows and meaningful metrics.
• Build or guide lightweight prototypes, benchmarks, methodology experiments, and internal tools to validate opportunities and accelerate solution development.
• Educate and mentor the broader FDE team on physical design concepts, EDA tooling, signoff methodology, and implementation trade-offs.
• Surface repeated customer signal to Product and Research to influence roadmap and platform capabilities.
• Progressively take on broader FDE responsibilities including solution architecture, prototype development, production deployment, and ownership of technical workstreams.

Minimum Qualifications

• BS with 7+ years, MS with 5+ years, or equivalent industry experience in physical design, physical implementation, or backend signoff for complex ASIC or SoC programs.
• Demonstrated success bringing complex designs through tapeout and hands-on experience in floorplanning, place and route, CTS, timing closure, power analysis, physical verification, and signoff.
• Deep familiarity with industry-standard EDA tools and flows for synthesis, place-and-route, static timing analysis (STA), physical verification, equivalence checking, and power analysis.
• Strong understanding of interactions between physical design and microarchitecture, RTL, verification, design methodology, libraries/PDKs, and system-level PPA trade-offs.
• Strong communication and collaboration skills and experience operating as a consultative expert and advisor.
• Strong scripting and automation skills in Python, Tcl, or similar.
• Willingness and enthusiasm to grow into a broader Forward Deployed Engineering role with hands-on solution building and customer-facing delivery.

Preferred Qualifications

• Experience across multiple semiconductor companies, design environments, or tool stacks.
• Prior customer- or partner-facing advisory, solutions engineering, or field engineering experience.
• Experience defining or scaling evaluation workflows, benchmarks, or acceptance criteria.
• Exposure to adjacent workflows such as design and/or verification.
• Experience applying AI/LLM systems to semiconductor workflows.

Notes

• This role is customer-facing and emphasizes both deep physical design expertise and the ability to help the organization deliver production-grade AI-enabled solutions in semiconductor contexts.